Feedback CS NMOS and Current mirror

We discussed feedback CS NMOS transistor for small signal output resistance and application in cross-coupled pair. Now we will turn to large signal analysis of the NMOS transistor. We need to establish DC voltages and currents in the circuit. We start with circuit shown in below figure.

 

We used a resistor R and constant DC voltage source VDD to provide DC points in the circuit. Since the drain and gate are tied together, the nmos always be in saturation. The current in the device is given by 

$$I_{D} = \frac{1}{2}\mu_{n}C_{ox}\frac{W}{L}(V_{GS} - V_{tn})^2$$ 

From KVL the voltage at drain(and gate) is given by

$$V_{GS} = V_{D} = V_{DD} - I_{D}R$$

If we draw these characteristics we will get curves as shown in the above figure. From the equations it is clear that the circuit is in negative feedback configuration. If the drain voltage increases the drain current will increase which in turn decrease the drain voltage. Due to this feedback, the circuit will attain a stable DC point on the curve, which establishes a constant voltage VGS and a reference current IREF. If we connect gate of another similar NMOS to the gate/drain of this transistor, same current IREF will flow in second transistor provided its drain voltage is greater than its gate voltage by Vtn.   

Now we modify the circuit by replacing the resistor with an ideal constant current source. We have to choose the value of the current IREF for required gm and ro. This constant current will keep on charging the drain node till an equal current is established in the transistor to balance. This will establish a corresponding gate voltage given by

$$V_{GS} = \sqrt{\frac{2 I_{REF}}{\mu C_{ox} \frac{W}{L}}} - V_{Tn}$$

We can use these circuits to produce copies of IREF in other circuits by using the  gate-source voltage established by IREF.

As we know the MOS transistors are voltage controlled current devices, i.e., provide the input voltage at gate, corresponding current will flow through the device. => Voltage is cause and current is response. If we see the above circuits at first place it seems that we inject a drain current IREF and get gate voltage in response like in current controlled voltage device, which is not true. Due to the negative feedback configuration only the gate/drain voltage happens to be established, where the device is still voltage controlled current source.