Frequency Response of Amplifiers -1

Let us analyze the following amplifier "differential pair with current mirror" and guess the frequency response  

First we find the nodes of interest in the small signal / ac equivalent circuit of the above. The source nodes of $M_{1}$ and $M_{2}$ are connected to ac ground. The remaining nodes are X and Y. 

Impedance @ node X is $$\frac{1}{g_{m3}}||r_{o1}||r_{o3} =\frac{1}{g_{m3}} $$

Impedance @ node Y is $$r_{o2}||r_{o4}$$

From this we can see node X has lower impedance compared to that of node Y. Therefore the pole at the output node (Y) is lower than the pole at node X.

Dominant pole is at output node $$ \boxed{\omega_{p1} = \frac{1}{(r_{o2}||r_{o4})C_{Y}}}$$ 

Non-dominant pole is at node X $$ \boxed{\omega_{p2} = \frac{g_{m3}}{C_{X}}}$$ 

[Note: $^{\dagger}$"Operational Transconductance Amplifier(OTA) can be defined as an amplifier where all nodes are low impedance except the input and output nodes". By this definition our amplifier is an OTA ]

From the circuit topology we can see that, from the input $v_{in}$ to $v_{out}$ there are two signal paths in parallel. One is fast path ($M_{1},M_{2}$) and second is slow path ($M_{1},M_{3},M_{4}$).

$$ \frac{V_{out}}{V_{in}} = \frac{A_{0}}{1+\frac{s}{\omega_{p1}}} + \frac{A_{0}}{(1+\frac{s}{\omega_{p1}})(1+\frac{s}{\omega_{p2}})} $$
$$\boxed{\frac{V_{out}}{V_{in}} =\frac{A_{0}(2+\frac{s}{\omega_{p2}})}{(1+\frac{s}{\omega_{p1}})(1+\frac{s}{\omega_{p2}})}}$$ Where $A_{0}$ is dc gain.
From the transfer function we see a left-hand side zero.  The following is the desired magnitude - frequency response of our amplifier. We want to push the non-dominant pole as far as possible after unity frequency - frequency where the magnitude reaches 0dB.

desired frequency response - magnitude

$\omega_{u}$ is unity frequency

Reference: Design of Analog CMOS Integrated Circuits,Razavi, B.
$\dagger$ CMOS: Circuit Design, Layout, and Simulation, R. Jacob Baker

Operational Transconductance Amplifier: OTA Basics - 1

Operational Transconductance Amplifier - OTA is a very important building block in analog design.

As we see from the previous posts the transconductance amplifier converts an input voltage to output current. The word "Operational" refers to the fact that it amplifies the difference voltage. The transconductance $g_{m} \propto I_{Bias} $

Using the OTA as a central element we can build application circuits like filters, voltage amplifiers, integrators etc. Here we will see a few filter/integrator circuits using OTA. 

We will find the transfer functions of these circuits intuitively without doing full analysis. The basic idea is 

1. The input voltage $V_{in}$ at input node causes an output current $i_{o}$. 
2. Output current $i_{o}$ flows through the resistance $r_{oeq}$seen at output node causing output voltage $V_{o} = i_{o} r_{oeq} $       

Lets see the recipe for finding the transfer function

1. Short the output to the ground and find the conductance seen at input node. Say $G_{m}(s) ^{\dagger}$.
2. Short the input to the ground and find the conductance seen at the output node. Say $G_{o}(s)$
3. Transfer function is $$\frac{V_{o}(s)}{V_{in}(s)} = \frac{G_{m}(s)}{G_{o}(s)}$$

$^{\dagger}$ When the input is connected to inverting terminal the $g_{m}$ is replaced by $-g_{m}$ 

Figure 1 shows the integrators. 

For 1(a). The transconductance seen from input to output is $g_{m}$ and the conductance seen into the output node is $sC$. 

$$\therefore \begin{equation} \frac{V_{o}(s)}{V_{in}(s)} = \frac{g_{m}}{sC} \end{equation}$$ 

For 1(b). The transconductance seen from input to output is $g_{m} + sC_{2}$ and the conductance seen into the output node is $s(C_{1} + C_{2})$. 

$$\therefore \frac{V_{o}(s)}{V_{in}(s)} = \frac{g_{m} + sC_{2}}{s(C_{1} + C_{2})} $$ 

Whenever there are more than one paths for the signal we can expect zeros in the transfer function. In 1(b) there are two paths from the input to output via transconductance and capacitor $C_{2}$  

In both circuits in figure 1 have poles at origin. i.e., the 20dB rolloff starts soon after the 0Hz with $\infty$ DC gain. In 1(b) though there are two capacitors in the circuit they are in parallel w.r.t the output node and hence we have a first order transfer function rather than second order. 

Now we will see how to shift the pole away from the origin to increase the useful bandwidth. Refer to the figure 2. A resistor R is added to the output node in parallel with the capacitance. Since R is connected to output node and GND there is no change in the positions of the zeros in the transfer function. Only the position of the poles will change as the conductance seen at the output changed.  

Figure 2 shows the lossy - integrators.

For 2(a). The transconductance seen from input to output is $g_{m}$ and the conductance seen into the output node is $sC + \frac{1}{R}$. 

$$\therefore \begin{equation} \frac{V_{o}(s)}{V_{in}(s)} = \frac{g_{m}}{sC + \frac{1}{R}} \end{equation}$$ 

For 2(b). The transconductance seen from input to output is $g_{m} + sC_{2}$ and the conductance seen into the output node is $s(C_{1} + C_{2}) + \frac{1}{R}$. 

$$\therefore \frac{V_{o}(s)}{V_{in}(s)} = \frac{g_{m} + sC_{2}}{s(C_{1} + C_{2}) + \frac{1}{R}} $$ 

So far we have seen the first order transfer functions, now refer to the figure 3. The two capacitors are independent and see different resistances, giving the hint there will be two poles in the transfer function. 

The transconductance seen from input to output is $g_{m} + \frac{sC_{2}}{sC_{2}R_{2} + 1}$ and the conductance seen into the output node is $sC_{1} + \frac{1}{R_{1}} + \frac{sC_{2}}{sC_{2}R_{2} + 1}$. 

$$\therefore \frac{V_{o}(s)}{V_{in}(s)} = \frac{g_{m} + \frac{sC_{2}}{sC_{2}R_{2} + 1}}{sC_{1}+ \frac{1}{R_{1}} + \frac{sC_{2}}{sC_{2}R_{2} + 1}} $$ 

Lets verify the sanity of the above transfer function. If we put $R_{2} = 0 \Omega $ the transfer function reduces to the first order as of the circuit 2(b). 

Lets find the zeros and poles of the transfer function. Lets rewrite the transfer function 

$$\frac{V_{o}(s)}{V_{in}(s)} = \frac{g_{m} + s[C_{2}(g_{m}R_{2} + 1)]}{C_{1}C_{2}R_{2}s^{2} + s(C_{2} + C_{1}) + \frac{1}{R_{1}}} $$ 

We will apply quadratic root approximation to find the poles. When the roots of the quadratic equation $ax^{2} + bx + c = 0$ are far from each other say $|r_{1}| > 10| r_{2}| $ then $r_{1} = \frac{-b}{a}$ and $r_{2} = \frac{-c}{b}$. To make sure the above conditions valid assume $R_{1} >> R_{2} $ so that the non-dominant pole is very far away from the dominant pole. 

By using the above approximations 

• DC gain = $g_{m} R_{1}$
• zero $z_{1} = \frac{-1}{C_{2} (\frac{1}{g_{m}} || R_{2})}$
• dominant pole $p_{0} = \frac{-1}{(C_{1} + C_{2})R_{1}}$
• non-dominant pole $p_{1} = \frac{-1}{(\frac{C_{1}C_{2}}{C_{1}+C_{2}})R_{2}}$ 

• 0dB frequency $\omega_{u} = \frac{g_{m}}{C_{1} + C_{2}}$

For the system to be stable the relative positions of the poles and zeros are very important. In a second order system like above they should be $$ |p_{0}| \ll |p_{1}| , |z_{1}|$$ 

CMOS Inverter as transconductance

In my last post we saw how a CMOS inverter is used as transimpedance amplifier. Now we will see how it can be used as transconductance amplifier. We will arrive to a similar circuit but we take a different path this time. Lets look what is a transconductance. It converts the input voltage to output current. The differential transconductance amplifier symbol is usually drawn as shown in figure 1(a). A simple MOS transistor can act as transconductance amplifier as shown in figure 1(b) and (c)  

If the input is applied at the gate of the NMOS and the source is grounded, the output current will flow into the device. That means a negative of this current is flowing out of the device.

Lets look as figure 2(a). If the two transistors of the 

cmos inverter are operating in the saturation region, then for a small incremental input voltage on the gate will creates incremental currents in the two transistors. The effective transconductance of the inverter is sum of the individual transconductances of the transistors. 

To make sure that both transistors are operating in the saturation region, and for maximum swing we have to set the operating/DC voltages of the output and input to the same provided both transistors are balanced. (this can be easily obtained from VTCurve of the inverter).  

This can be simply obtained by connecting the input and output of the inverter as shown the figure 3(b). But the problem is that when we apply incremental voltage at the input it is directly connected to output. That means the feedback connection should not be there for incremental signals. To realize this we can modify the feedback connection by adding a very large resistor so that in the incremental view the feedback is seen as disconnected, whereas in biasing it will be there. See figure 4.

The ideal transconductance amplifier should output the current irrespective the output voltage or load. This analog building block is very much used in the design of the active filters where it is combined with elements like OPAMPs, capacitors and resistors. One example of band pass filter is shown in figure 5

$$ \frac{V_{out}(s)}{V_{in}(s)} = \frac{s t_{2}}{1 + s t_{2} + s^{2} t_{1} t_{2}}$$

where $$t_{1} = \frac{C_{2}}{G_{m1}}$$ and $$t_{2} = \frac{C_{1}}{G_{m2}}$$

CMOS Inverter and PIXEL (photo diode plus amplifier)

In previous post Feedback CS NMOS and current mirror, large signal analysis of drain connected NMOS is discussed. Same analysis will work for diode connected PMOS also.  

Both of them can be used to generate voltage reference given by respective reference currents and transistor sizes. Now play time. What if we connect the output nodes of each circuit together? 

   The currents and voltages will be adjusted such that both transistors are in saturation and KCL are obeyed. The actual currents in the transistors depend on the difference of reference currents and in turn determines the output node voltage.

 

This is CMOS inverter with a current flowing into the device and feedback. 

 If the net reference current is positive, implies more current is flowing in NMOS than that of PMOS. If $$ \mu_{n}C_{ox}(\frac{W}{L})_{n} = \mu_{p}C_{ox}(\frac{W}{L})_{p} $$ and $$ V_{tn} = |V_{tp}| $$ then the output voltage is higher that 0.5 Vdd.                        

If the reference current is negative, then we can see more current in PMOS than that of NMOS. Then the output is less that 0.5Vdd. If the reference current is larger in magnitude the output voltage will be either VDD or 0V. 

Lets say the output voltage $V_{o} = V_{M}$ is in the vicinity of Vdd/2. What if we add a small ac current $\delta I$ in parallel to the current source? 

Say $$\delta I = i_{0} sin(\omega t) $$. The output voltage will be $$V_{o} = V_{M} + (gain) \delta i_{0} sin(\omega t) $$ where $$ gain = \frac{1}{g_{mn}} || r_{on} || \frac{1}{g_{mp}} || r_{op} $$     

If we want maximum swing just remove the reference current. Then $$ V_{M} = \frac{V_{DD}}{2}$$

In this way the circuit a transresistance/transimpedance is implemented. 

 

This is very much used in high-speed fiber-optics interconnects as transimpedance amplifier with slight modification as shown in figure 5. Standard practice is to use the channel of the MOSFET as feedback resistor.  

This is called "pixel - photo diode plus amplifier".

Variants of this are possible to improve bandwidth and noise immunity. In place of feedback resistor, a voltage follower can be inserted to isolate the gate-source capacitance from photo diode and to increase the output drive capability. 

XCP Negative Impedance and very high gain differential amplifier

This post is continuation of a previous post Gm - boosted Cross Coupled Pair (XCP) and Negative Impedance
In the previous part we saw how to build Gm-boost circuit  and negative resistance by cross-coupled pair. From that post consider figure 2, let us  assume the gain A = 1 and output resistances of all transistors are infinite. The differential impedances are given by Zeq as shown in the below figure 1.

Lets play with above circuits. What if we connect these two circuits in parallel? Lets do that and see.

$$Z_{eq}  = \frac{2}{g_{m2} - g_{m1}} \to \infty$$

When the transistors are matched the differential impedance tends to infinite value. We can use this as active load to a pmos differential pair as shown in the figure 3. By this way we can get really very very high gain. 

The high gain is because of the incremental currents in the load are cancelling each other. But the swing limit of the output will be degraded compared to the normal diode connected nmos load.

  

Feedback CS NMOS and Current mirror

We discussed feedback CS NMOS transistor for small signal output resistance and application in cross-coupled pair. Now we will turn to large signal analysis of the NMOS transistor. We need to establish DC voltages and currents in the circuit. We start with circuit shown in below figure.

 

We used a resistor R and constant DC voltage source VDD to provide DC points in the circuit. Since the drain and gate are tied together, the nmos always be in saturation. The current in the device is given by 

$$I_{D} = \frac{1}{2}\mu_{n}C_{ox}\frac{W}{L}(V_{GS} - V_{tn})^2$$ 

From KVL the voltage at drain(and gate) is given by

$$V_{GS} = V_{D} = V_{DD} - I_{D}R$$

If we draw these characteristics we will get curves as shown in the above figure. From the equations it is clear that the circuit is in negative feedback configuration. If the drain voltage increases the drain current will increase which in turn decrease the drain voltage. Due to this feedback, the circuit will attain a stable DC point on the curve, which establishes a constant voltage VGS and a reference current IREF. If we connect gate of another similar NMOS to the gate/drain of this transistor, same current IREF will flow in second transistor provided its drain voltage is greater than its gate voltage by Vtn.   

Now we modify the circuit by replacing the resistor with an ideal constant current source. We have to choose the value of the current IREF for required gm and ro. This constant current will keep on charging the drain node till an equal current is established in the transistor to balance. This will establish a corresponding gate voltage given by

$$V_{GS} = \sqrt{\frac{2 I_{REF}}{\mu C_{ox} \frac{W}{L}}} - V_{Tn}$$

We can use these circuits to produce copies of IREF in other circuits by using the  gate-source voltage established by IREF.

As we know the MOS transistors are voltage controlled current devices, i.e., provide the input voltage at gate, corresponding current will flow through the device. => Voltage is cause and current is response. If we see the above circuits at first place it seems that we inject a drain current IREF and get gate voltage in response like in current controlled voltage device, which is not true. Due to the negative feedback configuration only the gate/drain voltage happens to be established, where the device is still voltage controlled current source. 

Gm - boosted Cross Coupled Pair (XCP) and Negative Impedance

In this post we will take the concepts introduced in the previous posts further. In the last post we discussed the resistance look into drain when a voltage amplifier is inserted between the drain and the gate of NMOS transistor (figure 1a). Refer to figure 1a right part, to calculate output resistance we applied a positive voltage vx to the output node. If the gain A > 0, a positive current Ix will flow out from the voltage source confirming that Req is positive. Now we apply a negative voltage -vx to the drain and for A > 0 as shown in figure 1b left. The current Ix flow out of the transistor drain.

Differential circuit

We combine these two circuits and make a differential pair. The voltage sources are connected in opposite with respective to the ground. And moreover the same current is flowing through each voltage source and resulting no current to ground (Refer figure 2a). The differential impedance looking into two drains is given by Zeq, which is twice the value we obtained in previous circuit. Since the positive Vx still results in positive Ix, Zeq is positive impedance. 

Now let us play with the circuit. Instead of applying input to the voltage amplifier from the same voltage source, let apply from other voltage source, i.e., the cross coupling. Now the current Ix flows in opposite direction. For each NMOS, when the voltage at drain node increases (or decreases) the voltage at its gate decreases (or increases) resulting the trans-impedance current flow out of drain (or into the drain). Since positive Vx result in negative Ix, the differential impedance is negative. 

The last circuit is well known "Gm - boosted Cross Coupled Pair (XCP)"  circuit which has many applications in RF electronics, memory sense amplifiers etc.

  

Circuit intuitions: Example 2. Feedback CS NMOS

Let us analyze the effects of feedback in common source NMOS. Refer the below figure. (a) Shows the resistance looking into drain node when a voltage gain amplifier is inserted between the drain and gate of NMOS transistor. This output voltage is amplified and added to the input voltage. This is feedback circuit. 

If the input resistance of the voltage amplifier is infinite, then the output resistance is given by Req. 

Refer figure (b), the feedback gain is A = 1, the effective circuit is popular diode-connected NMOS where drain and gate are tied together.
Now  refer figure (c) when there is no feedback i.e., A = 0 the circuit is simply NMOS and the effective drain resistance is ro of NMOS.

• When A is greater than unity, it looks like g_m is increased by an amount A.G_m =A g_m  This is called g_{m -}boosting technique.

• When A is negative Req is negative.  Using this technique we can create negative resistances.

We will see the applications of the above two techniques in the future posts.

circuit intuitions: Example 1

Let us analyze the following circuit for resistance looking into the output node.

Let us identify the small blocks to analyze the whole circuit.

Block 1: Common source amplifier with load resistance.

Block 2: Voltage divider.

Gain of block 2 is A   = 1/2

Now for calculating the output resistance we use the concept discussed in the circuit intuitions article #2. The concept is shown in the above figure. The effective resistance seen at drain node is affected by the feedback gain A. In our example this feedback gain block is voltage divider.

R_out = 1/AG_m || R_o || R_L || (R₁ + R₂)*

= 1MΩ || 1MΩ || 1MΩ || 1MΩ = 250 k Ω   
* In our case the feedback gain block has input resistance which appears parallel to output node.